DC-DC converter

ABSTRACT

A DC-DC convertor includes a transformer having a primary winding adapted to be connected in series with a DC power source and a secondary winding, a rectifier and smoothing circuit, a main switching device, adapted to be connected in series with the DC power source, for connecting the rectifier and smoothing circuit to the secondary winding of the transformer when the main switching device is in an on-state, an auxiliary switching circuit connected in parallel with the main switching device, and a signal generating circuit for providing a first control signal to the main switching device and a second control signal to the auxiliary switching circuit. The auxiliary switching circuit includes a first capacitor connected in parallel with a second capacitor that is connected in series with an auxiliary switching device. The signal generating circuit controls on/off operation of the main switching device and the auxiliary switching device such that both the main switching device and the auxiliary switching device are in an off state simultaneously in a manner wherein the main switching device turns on after a first rest period has elapsed after the auxiliary switching device turns off and the auxiliary switching device turns on after a second rest period has elapsed after the main switching device turns off.

The present invention relates to the structure of a DC--DC converterdesigned to reduce losses.

BACKGROUND OF THE INVENTION

1. Description of the Prior Art

Recent developments in switching elements that can be used at highfrequencies have resulted in an increase in the switching frequencies ofDC--DC converters, and this in turn has led to expectations ofreductions in the size of DC--DC converters because it should now bepossible to construct smaller versions of the transformers, choke coils,and smoothing capacitors that take up so much room conventionally.

However, the switching losses that occur as current and voltage aresuperimposed whenever switching elements turn on and off increase asfrequencies increase. This means that, regardless of how small thesecomponents and other circuit elements become, at present the heatdissipation countermeasures necessary for coping with the heat generatedby switching losses ensure that sizes cannot be reduced further.

As the frequencies of DC--DC converters have increased, it has becomecommon to use insulated-gate field-effect transistors. However,insulated-gate field-effect transistors have the problem of parasiticcapacitances; if such a transistor is switched on or off while voltageis applied thereto, the parasitic capacitance causes a short circuit,which generates noise. Therefore, countermeasures against this noise arealso necessary.

A circuit diagram of a conventional forward DC--DC converter with oneswitching transistor is shown in FIG. 4, and the timings of voltage andcurrent waveforms in this DC--DC converter are shown in FIG. 5.

In this DC--DC converter, a DC source E_(s), a primary winding L₁ of atransformer T₁, and an insulated-gate field-effect transistor Q₁ thatacts as a switching element form a series circuit, and a rectifying andsmoothing circuit formed of a rectifier diode D₁, a flywheel diode D₂, achoke coil L₃, and a smoothing capacitor C₁ is connected to a secondarywinding L₂ of the transformer T₁.

The transistor Q₁ receives a gate voltage from a control circuit that isnot shown in the figure.

While the transistor Q₁ of the above DC--DC converter is on, a currentflows through the primary winding L₁ on the input side of thetransformer T₁, and a DC output is obtained at output terminals 1 and 1'from a voltage induced in the secondary winding L₂ on the output side,using the rectifying and smoothing circuit.

FIG. 5 shows the waveforms of the gate voltage V_(G1) of the transistorQ₁, the drain-source voltage V_(Q1) of the transistor Q₁, and thecurrent I_(Q1) flowing through the transistor Q₁ via the primary windingL₁, expressed against the same horizontal time axis. As can be seen fromthe figure, the drain-source voltage V_(Q1) and the current I_(Ql) aresuperimposed during a period between a time t₁ at which the transistorQ₁ turns on and a subsequent time t₂, and during a period between a timet₃ at which the transistor Q₁ turns off and a subsequent time t₄. Thissuperimposition causes power losses.

SUMMARY OF THE INVENTION

1. Purpose of the Present Invention

The object of the present invention is to provide a DC--DC converterwith one switching transistor in which losses can be reduced whenswitching elements are turned on and off.

2. Mode of Use of the Present Invention

The present invention relates to a DC--DC converter comprising a DCpower source, a primary winding of a transformer, and a main switchingelement connected in series,

whereby a DC output is extracted via a rectifier and smoothing circuitconnected to a secondary winding of the transformer.

The DC--DC converter is further provided with a main circuit comprisinga first capacitor and a series circuit of a second capacitor and anauxiliary switching element formed of an insulated gate field effecttransistor, both connected in parallel to the main switching element;and a signal generating circuit which generates gate signals for eachgate of the main switching element and the auxiliary switching element,

the gate signals providing a rest period during which switching elementsare off in such a manner that the main switching element turns on aftera first rest period has elapsed after the auxiliary switching elementhas turned off and the auxiliary switching element turns on after asecond rest period has elapsed after the main switching element hasturned off, wherein the first rest period is set to between 1/4 and 1/6of a resonance period determined by the inductance of the transformerand the first capacitor and the second rest period is set less than 1/2of the period during which the main switching element is off.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of an embodiment of the DC--DC converter ofthe present invention,

FIG. 2 is a circuit diagram of another embodiment of the DC--DCconverter of the present invention,

FIG. 3 is a timing chart of currents and voltages in the DC--DCconverter of FIG. 1,

FIG. 4 is a circuit diagram of a conventional DC--DC converter, and

FIG. 5 is a timing chart of currents and voltages in the DC--DCconverter of FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENT

An embodiment of the DC--DC converter of the present invention will bedescribed below with reference to FIG. 1. Elements in FIG. 1 that arethe same as those in FIG. 4 are denoted by the same reference notation.

FIG. 1 shows a DC--DC converter with one switching transistor whichtransfers power from a primary winding to a secondary winding during aperiod in which a main switching element is on. It comprises a seriescircuit of a DC source E_(s), a primary winding L₁ of a transformer T₁,and an n-channel insulated-gate field-effect transistor Q₁ that acts asa main switching element, with a rectifying and smoothing circuit formedof a rectifier diode D₁, a choke coil L₃, and a smoothing capacitor C₁being connected to a secondary Winding L₂ of the transformer T₁.

A first capacitor C₃ and a series circuit formed of a second capacitorC₄ and a p-channel insulated-gate field-effect transistor Q₂ are bothconnected in parallel to the transistor Q₁. The transistor Q₂ acts as anauxiliary switching device, as will be described later. D₄ denotes aparasitic diode of the transistor Q₂ and C₂ denotes a parasiticcapacitor of the transistor Q₁.

Rest periods during which both switching elements are off are set insuch a way that the transistor Q₁ turns on after a first rest period haselapsed after the transistor Q₂ turns off, and the transistor Q₂ turnson after a second rest period has elapsed after the transistor Q₁ turnsoff, transistors Q₁ and Q₂ being applied gate voltages from signalgenerating circuit 2.

The operation of the DC--DC converter of the above construction will nowbe described with reference to the timing chart of FIG. 3.

FIG. 3 shows the waveforms of a gate voltage V_(G1) of the transistorQ₁, a gate voltage V_(G2) of the transistor Q₂, a drain-source voltageV_(Q1) of the transistor Q₁, a current I_(Q1) flowing from the drain tothe source of the transistor Q₁, a current I_(c3) flowing through thecapacitor C₃, a current I_(c4) flowing through the capacitor C₄, acurrent I_(D4) flowing through the parasitic diode D₄ of the transistorQ₂, and a current I_(Q2) flowing from the drain to the source of thetransistor Q₂, expressed against the same horizontal time axis.

First, at a time t₅ at which the transistor Q₁ turns off, the currentI_(Q1) flowing from the drain to the source of the transistor Q₁ fallsto zero, and a magnetizing current that was part Of the current flowingthrough the primary winding L₁ flows as an excitation current throughthe parasitic capacitor C₂ and the capacitor C₃, charging the parasiticcapacitor C₂ and the capacitor C₃.

Since the capacitor C₃ is connected in parallel to the transistor Q₁,the capacitance between the drain and source of the transistor Q₁ isadded thereto. The drain-source voltage V_(Q1) rises smoothly inaccordance with Equation (1) below, and there is no period during whichthe current I_(Q1) flowing from drain to source is superimposed thereon.

    V.sub.Q1 =I·t/(C.sub.2 +C.sub.3)                  (1)

In Equation (1), I is magnetizing current, t is time, C₂ is thecapacitance of the parasitic capacitor C₂, and C₃ is the capacitance ofthe capacitor C₃.

At a time t₆ at which the drain-source voltage V_(Q1) of the transistorQ₁ exceeds the voltage V_(C4) of the capacitor C₄ which has been chargedpreviously, the magnetizing current flowing along the path formed of thecapacitor C₄ and the parasitic diode D₄ of the transistor Q₂ starts tocharge the capacitor C₄. It should be noted that in normal operation thevoltage V_(c4) charged in the capacitor C₄ is higher than the voltageV_(ES) of the DC source E_(S).

At a time t₈ at which all of the magnetizing energy of the primarywinding L₁ of the transformer T₁ has been transferred to the capacitorC₄, the current I_(c4) flowing through the capacitor C₄ becomes zero.The period between the time t₅ and the time t₈ is 1/2 of the periodduring which the transistor Q₁ is off in normal operation.

At a time t₇ before the current I_(c4) becomes zero, the gate voltageV_(G2) is applied to the transistor Q₂, turning it on, to ensure thatafter the time t₈ the voltage of the capacitor C₄ is applied to theprimary winding L₁ through the transistor Q₂ as a voltage opposite tothat applied when the main switching element (the transistor Q₁) is on,in other words, as a voltage (V_(c4) -V_(ES)), and the primary windingL₁ is magnetized in the direction opposite to that when the transistorQ₁ is on. Thus, the current I_(c4) continues to flow from the capacitorC₄ after the point at which it became zero. This is the state after thetime t₈. The period between the time t₅ and the time t₇ is a second restperiod during which both transistors Q₁ and Q₂ are off, and it is set tobe 1/7 of the period during which the transistor Q.sub. 1 is off.

After the time t₈, the above magnetizing current flows in the oppositedirection as the current I_(c4) through the transistor Q₂, the capacitorC₄, and the primary winding L₁, thus the primary winding L₁ of thetransformer T₁ is magnetized in the opposite direction, and theresultant magnetizing energy is used to effect after a time t₉ at whichthe transistor Q₂ turns off, as will be described below.

Note that in FIG. 3 the current I_(c3) of the capacitor C₃, the currentI_(c4) of the parasitic diode D₄, and the current I_(Q2) of thetransistor Q₂ are denoted by (+) when they flow from the primary windingL₁ to the cathode of the DC source E_(s), and by (-) when they flow inthe opposite direction.

Next, at a time t₉, the transistor Q₂ turns off and the current I_(c4)of the capacitor C₄ and the current I_(Q2) of the transistor Q₂ becomezero. However, the magnetizing current tends to flow, so it flows as adischarging current from the parasitic capacitor C₂ of the transistor Q₁and the capacitor C₃. In FIG. 3, the charging current of the capacitorC₃ is denoted by the (+) side of the graph of the current I_(c3), andthe discharging current is denoted by the (-) side thereof.

After the time t₉, when the parasitic capacitor C₂ and the capacitor C₃are discharging, the voltages of this parasitic capacitor C₂ and thecapacitor C₃ achieve a sine-wave resonance waveform based on a transientphenomenon caused by the inductance of the primary winding L₁ and theparallel capacitances of the parasitic capacitor C₂ and the capacitorC₃, and said voltages reach a minimum at 1/4 of the period of theresonance. The voltage between the two ends of the parasitic capacitorC₂ and the capacitor C₃ is the drain-source voltage V_(Q1) of thetransistor Q₁, and it becomes zero just before a time t₁₀ at 1/4 of theabove resonance period.

When the discharge of the parasitic capacitor C₂ and the capacitor C₃ iscompleted, the magnetizing current transfers to flow through a parasiticdiode D₃ of the transistor Q₁. The dotted lines on the drain-sourcevoltage V_(Q1) graph of FIG. 3 show the above sine-wave resonancewaveform.

The period between the time t₉ and the time t₁₀ is a first rest periodduring which both of the transistors Q₁ and Q₂ are off.

At the time t₁₀ when the magnetizing current is flowing through theparasitic diode D₃, the transistor Q₁, which is the main switchingelement, turns on.

Since the drain-source voltage V_(Q1) becomes zero at the time t₁₀, thecapacitor C₃ and, of course, the parasitic capacitor C₂ are completelydischarged at that point, and hence the parasitic capacitor C₂ does notgenerate a short-circuit current when the transistor Q₁ turns on.

In this way, since the drain-source voltage V_(Q1) of the transistor Q₁becomes zero before the main switching element (the transistor Q₁) turnson, there is no period during which the voltage V_(Q1) and the currentI_(Q1) are superimposed, and thus there are no switching losses. Inaddition, no short-circuit current flows from the parasitic capacitorC₂.

At the time when the transistor Q₁ turns off, the magnetizing currentstransfer to the parasitic capacitor C₂ of the transistor Q₁ and thecapacitor C₃ connected in parallel to the parasitic capacitor C₂, so thedrain-source voltage V_(Q1) rises smoothly, and there is no periodduring which the current I_(Q1) and the voltage V_(Q1) are superimposed,as described above. Therefore, no switching losses occur in thetransistor Q₁.

Note that in the above embodiment of the present invention, the firstrest period is 1/4 of the resonance period that is determined by theinductance of the transformer T₁ and the capacitance of the firstcapacitor C₃ and parasitic capacitor C₂, and the second rest period is1/7 of the period during which the main switching element (thetransistor Q₁) is off. In practice, however, the first rest period couldbe set to anywhere between 1/4 and 1/6 of the resonance period and thesecond rest period could be set less than 1/2 of the period during whichthe main switching element (the transistor Q₁) is off, to have the sameeffect.

Another embodiment of the DC--DC converter of the present invention willbe described below with reference to FIG. 2. Elements in FIG. 2 that arethe same as those in FIG. 1 are denoted by the same reference notation.

The embodiment of FIG. 2 differs from that of FIG. 1 in that the firstcapacitor C₃ and a series circuit of the second capacitor C₄ and atransistor Q₃ that acts as an auxiliary switching element are bothconnected in parallel in the sense of AC circuit theory to thetransistor Q₁ via the DC source E_(S). D₄ denotes a parasitic diode ofthe transistor Q₃.

Both of the currents flowing through the capacitor C₃ and the capacitorC₄ are AC so AC circuit theory informs that the first capacitor C₃ andthe series circuit of the second capacitor C₄ and the transistor Q₃should be connected in parallel to the transistor Q₁, because theimpedance of the DC source E_(s) is zero. In this case, the transistorQ₃ that acts as the auxiliary switching element should be an n-channelinsulated-gate field-effect transistor, from the viewpoint of DC appliedvoltage.

The overall operation of this embodiment of the present invention is thesame as that of the embodiment shown in FIG. 1, and the effect obtainedthereby is also the same.

It should be noted that the present invention can be applied to bothself-excited and IC driven systems.

EFFECT OF THE PRESENT INVENTION

As described above, in the DC--DC converter of the present invention,the voltage between the two ends of a main switching element is zerowhen that main switching element turns on, so that there is no periodduring which voltage and current are superimposed in the main switchingelement, and hence no switching losses occur therein. In addition, thevoltage between the two ends of the main switching element is zero whenthe parasitic capacitance of the main switching element has beendischarged, so no current flows to short-circuit the parasiticcapacitance within the main switching element, and hence no noiseoccurs.

When the main switching element turns off, the magnetizing currenttransfers to the first capacitor connected in parallel to the mainswitching element and the parasitic capacitance of the main switchingelement, so the voltage between the two ends of the main switchingelement rises smoothly, there is no period during which the voltageapplied to the main switching element and current are superimposed, andhence no switching losses occur therein.

Therefore, since there is no need to provide much in the way ofheat-dissipating countermeasures to cope with heat generated byswitching losses, the present invention enables the provision of acompact-sized but highly efficient DC--DC converter. In addition, sinceno noise caused by the short-circuit of the parasitic capacitance of themain switching element is generated, the present invention has theadvantage of providing a low-noise DC--DC converter.

What is claimed is:
 1. A DC--DC convertor comprising:a transformerhaving a primary winding adapted to be connected in series with a DCpower source and a secondary winding; a rectifier and smoothing circuit;a main switching means, adapted to be connected in series with said DCpower source, for connecting said rectifier and smoothing circuit tosaid secondary winding of said transformer when said main switchingmeans is in an on-state; an auxiliary switching circuit connected inparallel with said main switching means, said auxiliary switchingcircuit comprising a first capacitor connected in parallel with a secondcapacitor that is connected in series with an auxiliary switchingdevice; and a signal generating circuit means for providing a firstcontrol signal to said main switching means and a second control signalto said auxiliary switching device to control on/off operation of saidmain switching means and said auxiliary switching device such that bothsaid main switching means and said auxiliary switching device are in anoff-state simultaneously in a manner wherein said main switching meansturns on after a first rest period has elapsed after said auxiliaryswitching device turns off and said auxiliary switching device turns onafter a second rest period has elapsed after said main switching meansturns off, said first rest period being between 1/4 and 1/6 of aresonance period determined by an inductance of said transformer andsaid first capacitor, and said second rest period being less than 1/2 ofa period during which said main switching means is in an off-state.
 2. ADC--DC converter according to claim 1, wherein one end of each of saidfirst capacitor and said second capacitor connected in series with saidauxiliary witching device is connected to said primary winding andanother end of said first capacitor and said auxiliary switching deviceis adapted to be connected to a positive terminal of the DC powersource, whereby said first capacitor and said second capacitor connectedin series with said auxiliary switching device are connected in parallelwith said main switching means and are adapted to be connected inparallel with the DC power source.
 3. A DC--DC converter according toclaim 1, wherein said main switching means comprises an n-channelinsulated-gate field effect transistor (IGFET), said auxiliary switchingdevice comprises a p-channel IGFET, said first signal output from saidsignal generating means is provided to a gate of said n-channel IGFET,and said second signal output from said signal generating means isprovided to a gate of said p-channel IGFET.
 4. A DC--DC convertoraccording to claim 1, wherein said main switching means comprises ann-channel insulated-gate field effect transistor (IGFET) having a sourcewhich is adapted to be connected to a positive terminal of the DC powersupply, and said auxiliary switching device comprises a p-channel IGFET.